In this artilce, we are going to cover about how does DRAM work? as well as DRAM operations (Read and Write) with ease. Making ensure that at the end of this post; you will definitely fully learn about DRAM Working Operations without getting any hassle.
DRAM operations are done with using of single capacitor and transistor and their operations are totally depended on the charging stored on the capacitor. DRAM was invented by Robert Dennard in 1966, at IBM.
Working of DRAM
Dynamic Random Access Memory (DRAM) uses two elements as a storage cell like as transistor and capacitor. To keep charge or discharge of capacitors to be used the transistor. If logic high or “1” it means capacitor is fully charged otherwise it is discharged then its logic low or “0”. All operations of charging or discharging are performed by work line and bit line. Show in figure
DRAM Circuit Block Diagram
DRAM Read and Write Operations
There are two functions of DRAM; like as
- Write operation
- Reading Operation
In this operation, Voltage is supplied on bit line as well as signal is supplied on the address line for closing the transistor.
While storing the information on the cell, then transistor is turned on and voltage is supplied for bit line. Due to this process, some charge is stored in the capacitors. After some time transistor is turned off mode, and it goes to discharge. Hence, entire information is stored in the cell which can be read easily.
There are various lines which are used in the Read and Write Operations; such as –
- /CAS, the Column Address Strobe: This line helps to choose the column to be addressed. Address inputs are obtained on the falling edge of/CAS. It gets to enable a column that is chosen from the open row for getting read or write operations.
- /OE, Output Enable: The /OE gets to use, if controlling several memory chips in parallel form. It helps to handle the output to data I/O pins. If /RAS and /CAS get to low, /WE is high, and /OE is also getting low, then data pins are driven by DRAM chip.
- /RAS, the Row Address Strobe: The /RAS line selects the row to be addressed. Address inputs are obtained on the falling edges of the /RAS line. The row is getting to open as long as /RAS remains low.
- /WE, Write Enable: The signal monitors that falling edge of /CAS is read or writes. High enables a read action but low enables the write action. Data inputs are also captured on the falling edge of /CAS.
Other Operations of DRAM Memory
Charge Loss: DRAM cells store data in the form of electrical charges. Over time, these charges can leak, leading to data loss.
Periodic Refresh: To prevent data loss, DRAM requires periodic refreshing. During refresh operations, the memory controller reads and rewrites the data in each memory cell, restoring the charge and preventing information loss.
Row Deactivation: After a read or write operation, the activated row needs to be deactivated to prepare for the next access.
Precharging: The precharge operation resets the memory cells in the activated row, preparing the DRAM for the next access by making it ready for the activation of a different row.
RAS (Row Address Strobe) and CAS (Column Address Strobe):
RAS Signal: Row Address Strobe is a control signal that indicates the beginning of a row access operation.
CAS Signal: Column Address Strobe is a control signal that indicates the beginning of a column access operation.
Automatic Refresh: Some DRAM modules support automatic refresh, where the memory controller automatically performs refresh operations without the need for explicit commands. This helps in maintaining data integrity without impacting regular read and write operations.
Key Components of DRAM Memory
DRAM memory consists of various components, and each playing a specific role to storage and retrieval of data. Here are the main components of DRAM, including:
Memory Cells: Each bit of data is stored in a memory cell, typically consisting of a capacitor and a transistor. The capacitor holds the charge, representing the binary state (0 or 1), and the transistor controls the access to the stored data.
Rows and Columns: DRAM is organized into a matrix of rows and columns, forming an array of memory cells. Each row and column has a unique address.
Address Bus: The address bus carries signals that specify the location (row and column) of the data to be read from or written to in the DRAM array. The memory controller uses these signals to select the appropriate row and column during read or write operations.
Data Bus: The data bus is used to transfer data between the DRAM and the memory controller. During read operations, data is sent from the DRAM to the memory controller, and during write operations, data is sent from the memory controller to the DRAM.
Row Decoder: The row decoder interprets the row address signals from the address bus and selects the specific row in the DRAM array for activation.
Column Decoder: The column decoder interprets the column address signals from the address bus and selects the specific column in the activated row for reading or writing data.
Sense Amplifiers: Sense amplifiers amplify the weak signals read from the memory cells, ensuring that the data can be accurately interpreted by the memory controller.
Write Drivers: Write drivers amplify and drive the data signals to the selected memory cells during write operations.
Refresh Circuitry: DRAM cells are volatile, and their content degrades over time. Refresh circuitry automatically reads and rewrites data in each row periodically to prevent data loss.
Memory Controller: The memory controller manages the flow of data between the CPU and the DRAM. It interprets memory access requests, generates the necessary control signals, and ensures the proper timing of read and writes operations.
Clock Signal: A clock signal helps synchronize the timing of various operations within the DRAM and ensures proper coordination with the rest of the system.
These components work together and perform many functions, including read, write, refresh, hold, and more; which are most necessary for the functioning of DRAM in computer system.
Major Functions of DRAM Memory
The main functions of DRAM (Dynamic Random Access Memory) are:
- Storing data for a computer processor to function
- Providing fast access to data for the processor, enabling quick execution of instructions
- Storing program code that is needed by the processor
- Serving as the main memory in modern computers and graphics cards
- Being used in various portable devices and video game consoles
- Allowing for high-capacity, low-cost memory storage in digital electronics
How to Organize DRAM?
Today’s, Dynamic RAM is available in different types of forms but it depends upon their applications; for example – DIMM (Dual Inline Memory Module) consists several onboard DRAM chips.
These types of DIMMs have 1 GB memory, but you can see “2Rx8” written on the sticker. 2R represents that this module comes in rank 2, but x8 mean and that output width of data coming from every DRAM chips. A rank is a individual addressable group of DRAMs. In this scenario, one rank is group of four DRAM chips, but we have 2 ranks if there are 8 total.
DIMM has higher level of organization with getting of DRAM’s rank. Mention in the figure that, every chip is organized into number of memory arrays and banks, and columns. Show in the image, DRAM chip has four banks.
Each bank works individually to the others, it means all operations such as reading, writing, and pre-recharging can be performed on bank without stressing to other.
FAQs (Frequently Asked Questions)
What is the operation of DRAM cell?
The operation of DRAM cell involves the use of a capacitor to store data. A DRAM memory cell is a capacitor that is charged to represent a 1 or discharged to represent a 0. The presence or absence of charge on the capacitor determines the logic state of the cell.
What is the read and write operation of 1T DRAM?
The read and write operation of 1T DRAM (1 Transistor DRAM) involves the use of a single transistor and a capacitor to store data. The transistor acts as a switch that controls the flow of charge to the capacitor.
What is the purpose of the refresh operation in DRAM?
The refresh operation is necessary to compensate for charge leakage in DRAM cells. It involves reading and rewriting the data in each row periodically to prevent data loss over time.
How does DRAM interact with the memory controller?
DRAM makes the interaction along with the memory controller that is responsible for managing the flow of data in between the CPU and DRAM memory. The memory controller generates the necessary signals for addressing, reading, and writing data in DRAM.
How does DRAM contribute to overall system performance?
DRAM plays the major role in system performance with offering the fastest and temporary storage for actively used program code and data. With using the high-speed, it lets the CPU to instantly retrieve and manipulate information; and impacting the overall responsiveness of the system.
Through this post, you have been completely aware about how does DRAM work as well as DRAM operations (Read and Write) with ease. If this post is useful for you, then please share it along with your friends, family members or relatives over social media platforms like as Facebook, Instagram, Linked In, Twitter, and more.
If you have any experience, tips, tricks, or query regarding this issue? You can drop a comment!