DRAM operations are done with using of single capacitor and transistor and their operations are totally depended on the charging stored on the capacitor.
DRAM was invented by Robert Dennard in 1966, at IBM.
Working of DRAM
Dynamic Random Access Memory (DRAM) uses two elements as a storage cell like as transistor and capacitor. To keep charge or discharge of capacitors to be used the transistor. If logic high or “1” it means capacitor is fully charged otherwise it is discharged then its logic low or “0”. All operations of charging or discharging are performed by work line and bit line. Show in figure
DRAM Operations Are
There are two functions of DRAM; like as
- Write operation
- Reading Operation
In this operation, Voltage is supplied on bit line as well as signal is supplied on the address line for closing the transistor.
While storing the information on the cell, then transistor is turned on and voltage is supplied for bit line. Due to this process, some charge is stored in the capacitors. After some time transistor is turned off mode, and it goes to discharge. Hence, entire information is stored in the cell which can be read easily.
There are various lines which are used in the Read and Write Operations; such as –
- /CAS, the Column Address Strobe: This line helps to choose the column to be addressed. Address inputs are obtained on the falling edge of/CAS. It gets to enable a column that is chosen from the open row for getting read or write operations.
- /OE, Output Enable: The /OE gets to use, if controlling several memory chips in parallel form. It helps to handle the output to data I/O pins. If /RAS and /CAS get to low, /WE is high, and /OE is also getting low, then data pins are driven by DRAM chip.
- /RAS, the Row Address Strobe: The /RAS line selects the row to be addressed. Address inputs are obtained on the falling edges of the /RAS line. The row is getting to open as long as /RAS remains low.
- /WE, Write Enable: The signal monitors that falling edge of /CAS is read or writes. High enables a read action but low enables the write action. Data inputs are also captured on the falling edge of /CAS.
How to Organize DRAM?
Today’s, Dynamic RAM is available in different types of forms but it depends upon their applications; for example – DIMM (Dual Inline Memory Module) consists several onboard DRAM chips.
These types of DIMMs have 1 GB memory, but you can see “2Rx8” written on the sticker. 2R represents that this module comes in rank 2, but x8 mean and that output width of data coming from every DRAM chips. A rank is a individual addressable group of DRAMs. In this scenario, one rank is group of four DRAM chips, but we have 2 ranks if there are 8 total.
DIMM has higher level of organization with getting of DRAM’s rank. Mention in the figure that, every chip is organized into number of memory arrays and banks, and columns. Show in the image, DRAM chip has four banks.
Each bank works individually to the others, it means all operations such as reading, writing, and pre-recharging can be performed on bank without stressing to other.